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datasheet 9fgl08 october 19, 2016 1 ?2016 integrated device technology, inc. 8-output 3.3v pcie clock generator 9fgl08 description the 9fgl08 devices are 3.3v members of idt's 3.3v full-featured pcie family. the devices have 8 output enables for clock management and support 2 different spread spectrum levels in addition to spread off. the 9fgl08 supports pcie gen1-4 common clocked architectures (cc) and pcie separate reference no-spread (srns) and separate reference independent spread (sris) clocking architectures. the 9fgl08p1 can be programmed with a user-defined power up default smbus configuration. recommended application pcie gen1-4 clock generation for riser cards, storage, networking, jbod, communications, access points output features ? 8 ? 100 mhz low-power hcsl (lp-hcsl) dif pairs ? 9fgl0841 default z out = 100 ? ? 9fgl0851 default z out = 85 ? ? 9fgl08p1 factory programmable defaults ? 1 - 3.3v lvcmos ref output w/wake-on-lan (wol) support ? easy ac-coupling to other logic families, see idt application note an-891 key specifications ? pcie gen1-2-3-4 cc-compliant ? pcie gen2-3 sris-compliant ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif 12k-20m phase jitter is <2ps rms when ssc is off ? ref phase jitter is <300fs rms, ssc off, and <1.5ps rms, ssc is on ? 100ppm frequency accuracy on all clocks features/benefits ? direct connection to 100 ? (xx41) or 85 ? (xx51) transmission lines; saves 32 resistors compared to standard pcie devices ? 206mw typical power consumption (62ma*3.3v); eliminates thermal concerns ? smbus-selectable features allows optimization to customer requirements: ? control input polarity ? control input pull up/downs ? slew rate for each output ? differential output amplitude ? 33, 85 or 100 ? output impedance for each output ? spread spectrum amount ? 41 and 51 devices contain default configuration; smbus interface not required for device operation ? p1 device allows factory progr amming of customer-defined input/output frequencies and smbus power up default; allows exact optimization to customer requirements. ? 8mhz - 40mhz input frequency with 9fgl08p1 device (25mhz default); flexibility ? oe# pins; support dif power management ? pin/smbus selectable 0%, -0.25% or -0.5% spread on dif outputs; minimize emi and phase jitter for each application ? dif outputs blocked until pll is locked; clean system start-up ? two selectable smbus addresse s; multiple devices can easily share an smbus segment ? space saving 48-pin 6x6mm vfqfpn; minimal board space block diagram note: resistors default to internal on 41/51 devices. p1 devices ha ve programmable default impedances on an output-by-output basis. xin/clkin_25 x2 vss_en_tri ^ckpwrgd_pd# sdata_3.3 ref voe(7:0)# sclk_3.3 vsadr 8 603-25-150ja4i 25mhz ssc capable pll control logic dif0 dif1 dif2 dif3 dif4 dif5 dif6 dif7
8-output 3.3v pcie clock generator 2 october 19, 2016 9fgl08 datasheet pin configuration smbus address selection table power management table 3 power connections ^ckpwrgd_pd# vddio voe7# dif7# dif7 voe6# dif6# dif6 gnd vddio vdd3.3 voe5# 48 47 46 45 44 43 42 41 40 39 38 37 vss_en_tri 1 36 dif5# gndxtal 2 35 dif5 xin/clkin_25 3 34 voe4# x2 4 33 dif4# vddxtal3.3 5 32 dif4 vddref3.3 6 31 vddio vsadr/ref3.3 7 30 vdda3.3 gndref 8 29 gnda gnddig 9 28 voe3# sclk_3.3 10 27 dif3# sdata_3.3 11 26 dif3 vdddig3.3 12 25 voe2# 13 14 15 16 17 18 19 20 21 22 23 24 vddio voe0# dif0 dif0# voe1# dif1 dif1# vdd3.3 vddio gnd dif2 dif2# vv prefix indicates internal 60kohm pull down resistor v prefix indicates internal 120kohm pull down resistor ^ prefix indicates internal 120kohm pull up resistor 48-pin vfqfpn, 6x6 mm, 0.4mm pitch 9fgl0841/51/p1 epad is gnd sadr address 0 1101000 1 1101010 state of sadr on first application of ckpwrgd_pd# + read/write bit x x true o/p comp. o/p 0xx low 1 low 1 hi-z 2 1 1 0 running running running 111 disabled 1 disabled 1 running 10x disabled 1 disabled 1 disabled 4 1. the output state is set by b11[1:0] (low/low default) 3. input polarities defined at default values for 9fgl0841/0851. 4. see smbus description for byte 3, bit 4 ref ckpwrgd_pd# smbus oe bit 2. ref is hi-z until the 1st assertion of ckpwrgd_pd# high. after this, when ckpwrg_pd# is low, ref is disabled unless byte3[5]=1, in which case ref is running.. difx/difx# oex# pin pin number vdd vddio gnd 52 xtal osc 68ref power 12 9 digital (dirty) power 20,38 13,21,31,39, 47 22,29,40, 49 dif outputs 30 29 pll analog description
october 19, 2016 3 8-output 3. 3v pcie clock generator 9fgl08 datasheet pin descriptions pin # pin name type description 1vss_en_tri latched in latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, m = -0.25%, 0 = spread off 2 gndxtal gnd gnd for xtal 3 xin/clkin_25 in crystal input or reference clock input. nominally 25mhz. 4 x2 out crystal output. 5 vddxtal3.3 pwr power supply for xtal, nominal 3.3v 6 vddref3.3 pwr vdd for ref output. nominal 3.3v. 7vsadr/ref3.3 latched i/o latch to select smbus address/3.3v lvcmos copy of x1/refin pin 8 gndref gnd ground pin for the ref outputs. 9 gnddig gnd ground pin for digital circuitry 10 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 11 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 12 vdddig3.3 pwr 3.3v digital power (dirty power) 13 vddio pwr power supply for differential outputs 14 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 15 dif0 out differential true clock output 16 dif0# out differential complementary clock output 17 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 vdd3.3 pwr power supply, nominal 3.3v 21 vddio pwr power supply for differential outputs 22 gnd gnd ground pin. 23 dif2 out differential true clock output 24 dif2# out differential complementary clock output 25 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 26 dif3 out differential true clock output 27 dif3# out differential complementary clock output 28 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 29 gnda gnd ground pin for the pll core. 30 vdda3.3 pwr 3.3v power for the pll core. 31 vddio pwr power supply for differential outputs 32 dif4 out differential true clock output 33 dif4# out differential complementary clock output 34 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 35 dif5 out differential true clock output 36 dif5# out differential complementary clock output 37 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 38 vdd3.3 pwr power supply, nominal 3.3v 39 vddio pwr power supply for differential outputs
8-output 3.3v pcie clock generator 4 october 19, 2016 9fgl08 datasheet pin descriptions, cont. test loads alternate terminations the 9fgl family can ea sily drive lvpecl, lvds, and cml logic. see ?an-891 driving lvpecl, lvds, and cml logic with idt's "universal" low-power hcsl outputs? for details. pin # pin name type description 40 gnd gnd ground pin. 41 dif6 out differential true clock output 42 dif6# out differential complementary clock output 43 voe6# in active low input for enabling dif pair 6. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 44 dif7 out differential true clock output 45 dif7# out differential complementary clock output 46 voe7# in active low input for enabling dif pair 7. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 47 vddio pwr power supply for differential outputs 48 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 49 epad gnd connect to ground. ref output 33 ref output test load 5pf zo = 50 ohms rs rs low-power differential output test load 2pf 2pf 5 inches zo=100ohm note: the device can drive transmission line lengths greater than those specified by the pcie sig terminations device zo ( ? )rs ( ? ) 9fgl0841 100 none needed 9fgl0851 100 7.5 9fgl08p1 100 prog. 9fgl0841 85 n/a 9fgl0851 85 none needed 9fgl08p1 85 prog.
october 19, 2016 5 8-output 3. 3v pcie clock generator 9fgl08 datasheet absolute maximum ratings stresses above the ratings listed below ca n cause permanent damage to the 9fgl08. t hese ratings, which are standard values for idt commercially rated parts, are stress ratings only. function al operation of the device at these or any other conditions above those indicated in the operational sections of the specif ications is not implied. exposur e to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. electrical characteris tics?smbus parameters electrical characteristi cs?current consumption parameter symbol conditions min typ max units notes supply voltage vddx -0.5 4.6 v 1,2 input voltage v in -0.5 v dd +0.5 v 1,3 input high voltage, smbus v ihsmb smbus clock and data pins 3.9 v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2500 v 1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 4.6v. ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes smbus input low voltage v ilsmb v ddsmb = 3.3v 0.8 v smbus input high voltage v ihsmb v ddsmb = 3.3v 2.1 3.6 v smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb 2.7 3.6 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f smb smbus operating frequency 500 khz 2 1 guaranteed by design and characterization, not 100% tested in production. 2. the device must be powered up for the smbus to function. ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i ddaop vdda, all outputs active @100mhz 13 18 ma i ddop all vdd, except vdda and vddio, all outputs active @100mhz 19 26 ma i ddioop vddio, all outputs active @100mhz 31 40 ma i ddap d vdda, dif outputs off, ref output r unning 0.9 1.5 ma 1 i ddpd all vdd, except vdda and vddio, dif outputs off, ref output r unning 6.5 9ma1 i ddi op d vddio, dif outputs off, ref output running 0.05 0.1 ma 1 i ddap d vdda, all outputs off 0.9 1.5 ma i ddpd all vdd, except vdda and vddio, all outputs off 2.4 3ma i ddi opd vddio, all outputs off 0.05 0.1 ma 1 this is the current required to have the ref output running in wake-on-lan mode (byte 3, bit 5 = 1) powerdown current (power down state and byte 3, bit 5 = '0') operating supply current wake-on-lan current (power down state and byte 3, bit 5 = '1')
8-output 3.3v pcie clock generator 6 october 19, 2016 9fgl08 datasheet electrical characteristics?input/supply /common parameters?normal operating conditions ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddxxx supply voltage for core, analog and single-ended lvcmos outputs. 3.135 3.3 3.465 v io supply voltage vddio supply voltage for differential low power outputs. 0.9975 1.05-3.3 3.465 v ambient operating temperature t amb industrial range -40 25 85 c input high voltage v ih 0.75 v ddx v ddx + 0.3 v input low voltage v il -0.3 0.25 v ddx v input high voltage v ihtri 0.75 v ddx v dd + 0.3 v input mid voltage v imtri 0.4 v ddx 0.5 v ddx 0.6 v ddx v input low voltage v iltri -0.3 0.25 v ddx v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -50 50 ua input frequency f in xtal, or x1 input 8 25 40 mhz 4 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.3 1.8 ms 1,2 ss modulation frequency f mo d (triangular modulation) 30 31.6 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 12 3clocks1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 1,2 trise t r rise time of single-ended control inputs 5 ns 1,2 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. input current 4 the 9fglxxp1 devices can be programmed for various input frequencies from 8 to 40mhz. the 9fglxx41/51 devices use 25mhz. capacitance 3 time from deassertion until outputs are >200 mv single-ended inputs, except smbus single-ended tri-level inputs ('_tri' suffix)
october 19, 2016 7 8-output 3. 3v pcie clock generator 9fgl08 datasheet electrical characteristics? dif low-power hcsl outputs ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes scope avera g in g on, fast settin g 22.74 v/ns 2,3 scope averaging, slow setting 1 1.9 3 v/ns 2,3 crossing voltage (abs) vcross_abs scope averaging off 250 409 550 mv 1,4,5 crossing voltage (var) -vcross scope averaging off 14 140 mv 1,4,9 avg. clock period accuracy t period_avg -100 0.0 +2600 ppm 2,10,13 absolute period t period_abs includes jitter and spread spectrum modulation 9.94906 10.0 10.1011 ns 2,6 jitter, cycle to cycle t j c y c-c y c 16 50 ps 2 voltage high v hi gh 660 761 850 1 voltage low v low -150 -7 150 1 absolute max volta g e vmax 819 1150 1,7,15 absolute min voltage vmin -300 -46 1,8,15 duty cycle t dc 45 49.2 55 % 2 slew rate matching trf 6 20 % 1,14 skew, output to output t sk3 averaging on, v t = 50% 35 50 ps 2 2 measured from differential waveform. 8 defined as the minimum instantaneous volta g e includin g undershoot. 15 at default smbus amplitude settings. measurement on single ended signal using absolute value. (scope averaging off) mv slew rate trf mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) 14 matching applies to rising edge rate for refclk+ and falling edge rate for refclk-. it is measured using a 75 mv window cente red on the median cross point where refclk+ rising meets refclk- falling. the median cross point is used to calculate the voltage thre sholds the oscilloscope is to use for the edge rate calculations. the rise edge rate of refclk+ should be compared to the fall edge ra te of refclk-; the maximum allowed difference should not exceed 20% of the slowest edge rate. 1 measured from sin g le-ended waveform. 3 measured from -150 mv to +150 mv on the differential waveform (derived from refclk+ minus refclk-). the signal must be monotoni c through the measurement region for rise and fall time. the 300 mv measurement window is centered on the differential zero cross ing. 4 measured at crossing point where the instantaneous voltage value of the rising edge of refclk+ equals the fa lling edge of refclk-. 5 refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to a ll crossing points for this measurement. 6 defines as the absolute minimum or maximum instantaneous period. this includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum modulation. 7 defined as the maximum instantaneous volta g e includin g overshoot. 9 defined as the total variation of all crossing voltages of rising refclk+ and falling refclk-. this is the maximum allowed var iance in v cross for an y p articular s y stem. 10 refer to section 4.3.7.1.1 of the pci ex p ress base s p ecification , revision 3.0 for information re g ardin g ppm considerations. 11 system board compliance measurements must use the test load. refclk+ and refclk- are to be measured at the load capacitors cl. single ended probes must be used for measurements requiring single ended measurements. either single ended probes with math or differential probe can be used for differential measurements. test load cl = 2 pf. 12 t stable is the time the differential clock must maintain a minimum 150 mv differential voltage after rising/falling edges before it i s allowed to droo p back into the vrb 100 mv differential ran g e. 13 ppm refers to parts per million and is a dc absolute period accuracy specification. 1 ppm is 1/1,000,000th of 100.000000 mhz e xactly or 100 hz. for 300 ppm, then we have an error budget of 100 hz/ppm * 300 ppm = 30 khz. the period is to be measured with a frequen cy counter with measurement window set to 100 ms or greater. the 300 ppm applies to systems that do not employ spread spectrum clocking, or that use common clock source. for systems employing spread spectrum clocking, there is an additional 2,500 ppm nom inal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,800 ppm.
8-output 3.3v pcie clock generator 8 october 19, 2016 9fgl08 datasheet electrical characteristics?fi ltered phase jitter parameters - pc ie common clocked (cc) architectures electrical characteristics?filtered pha se jitter parameters - pcie separate reference independent spr ead (sris) architectures 3 electrical characteristics?dif lp-hcsl outp ut unfiltered pha se jitter parameters t amb = over the specified operating range. supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jphpcieg1-cc pcie gen 1 19 28 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz (pll bw of 5-16mhz or 8-5mhz, cdr = 5mhz) 0.4 0.6 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) (pll bw of 5-16mhz or 8-5mhz, cdr = 5mhz) 1.2 1.9 3.1 ps (rms) 1,2 t jphpcieg3-cc pcie gen 3 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.3 0.45 1 ps (rms) 1,2 t jphpcieg4-cc pcie gen 4 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.3 0.45 0.5 ps (rms) 1,2 1 applies to all outputs. phase jitter t jphpcieg2-cc 2 based on pcie base specification rev4.0 version 0.7draft. see http://www.pcisi g .com for latest specifications. 3 sample size of at least 100k cycles. this fi g ures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. t amb = over the specified operating range. supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jphpcieg2-sris pcie gen 2 (pll bw of 16mhz , cdr = 5mhz) 0.7 1.1 2 ps (rms) 1,2 t jphpcieg3-sris pcie gen 3 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.5 0.65 0.7 ps (rms) 1,2 1 applies to all outputs. 2 based on pcie base specification rev3.1a. these filters are different than common clock filters. see http://www.pcisig.com for latest specifications. there is a proposal to reduce the pcie gen3 limit to 0.5ps. 3 as of pcie base specification rev4.0 draft 0.7, sris is not currently defined for gen1 or gen4. phase jitter, pll mode ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units phase jitter, 12k-20m t jph12k20m 100mhz outputs with ref output enabled ssc off 1.5 2 n/a ps (rms)
october 19, 2016 9 8-output 3. 3v pcie clock generator 9fgl08 datasheet electrical characteristics? ref ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values ppm 1,2 clock period t p eriod ref output ns 2 high output voltage v hi gh i oh = -2ma 0.8xv ddre f v low output voltage v low i ol = 2ma 0.2xv ddre f v t rf1 byte 3 = 1f, v oh = 0.8*vdd, v ol = 0.2*vdd 0.5 0.9 1.5 v/ns 1 t rf1 byte 3 = 5f, voh = 0.8*vdd, vol = 0.2*vdd 1.0 1.5 2.5 v/ns 1,3 t rf1 byte 3 = 9f, voh = 0.8*vdd, vol = 0.2*vdd 1.5 2.1 3.1 v/ns 1 t rf1 byte 3 = df, voh = 0.8*vdd, vol = 0.2*vdd 2.0 2.7 3.8 v/ns 1 duty cycle d t1x v t = vdd/2 v 45 49.7 55 % 1,4 duty cycle distortion d tcd v t = vdd/2 v -1 0 0 % 1,5 jitter, cycle to cycle t j c y c-c y c v t = vdd/2 v 35 125 ps 1,4 t j dbc1k 1khz offset -145 -135 dbc 1,4 t j dbc10k 10khz offset to nyquist -150 -140 dbc 1,4 t jphref 12khz to 5mhz, dif ssc off 0.132 0.3 ps (rms) 1,4 t jphref 12khz to 5mhz, dif ssc on 1.4 1.5 ps (rms) 1,4 1 guaranteed by design and characterization, not 100% tested in production. 3 default smbus value 4 when driven by a crystal. 5 when driven by an external oscillator via the x1 pin, x2 should be floating. 2 all lon g term accuracy and clock period specifications are g uaranteed assumin g that ref is trimmed to 25.00 mhz 0 noise floor jitter, phase rise/fall slew rate 40
8-output 3.3v pcie clock generator 10 october 19, 2016 9fgl08 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: smbus address is latched on sadr pin. unless otherwise indicated, default values are for the xx41 and xx51. p1 devices are fully factory programmable. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
october 19, 2016 11 8-output 3.3v pcie clock generator 9fgl08 datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 dif oe7 output enable rw pin control 1 bit 6 dif oe6 output enable rw pin control 1 bit 5 dif oe5 output enable rw pin control 1 bit 4 dif oe4 output enable rw pin control 1 bit 3 dif oe3 output enable rw pin control 1 bit 2 dif oe2 output enable rw pin control 1 bit 1 dif oe1 output enable rw pin control 1 bit 0 dif oe0 output enable rw pin control 1 smbus table: ss readback and control register byte 1 name control function type 0 1 default bit 7 ssenrb1 ss e nable readback bit1 r latch bit 6 ssenrb1 ss e nable readback bit0 r latch bit 5 ssen_swcntrl e nable sw control of ss rw ss control locked values in b1[4:3] control ss amount. 0 bit 4 ssensw1 ss enable software ctl bit1 rw 1 0 bit 3 ssensw0 ss enable software ctl bit0 rw 1 0 bit 2 x bit 1 amplitude 1 rw 00 = 0.6v 01= 0.68v 1 bit 0 amplitude 0 rw 10 = 0.75v 11 = 0.85v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 slewratesel dif7 adjust slew rate of dif7 rw slow setting fast setting 1 bit 6 slewratesel dif6 adjust slew rate of dif6 rw slow setting fast setting 1 bit 5 slewratesel dif5 adjust slew rate of dif5 rw slow setting fast setting 1 bit 4 slewratesel dif4 adjust slew rate of dif4 rw slow setting fast setting 1 bit 3 slewratesel dif3 adjust slew rate of dif3 rw slow setting fast setting 1 bit 2 slewratesel dif2 adjust slew rate of dif2 rw slow setting fast setting 1 bit 1 slewratesel dif1 adjust slew rate of dif1 rw slow setting fast setting 1 bit 0 slewratesel dif0 adjust slew rate of dif0 rw slow setting fast setting 1 note: see "low-power hcsl outputs" table for slew rates. smbus table: nominal vhigh amplitude control/ ref control register byte 3 name control function type 0 1 default bit 7 rw 00 = slowest 01 =slow 0 bit 6 rw 10 = fast 11 = fastest 1 bit 5 ref power down function wake-on-lan enable for ref rw ref disabled in power down ref runs in power down 0 bit 4 ref oe ref output enable rw disabled 1 enabled 1 bit 3 x bit 2 x bit 1 x bit 0 x 1. the disabled state depends on byte11[1:0]. '00' = low, '01'=hiz, '10'=low, '11'=high byte 4 is reserved reserved 1. a low on these bits will overide the oe# pin and force the differential output to the state indicated by b11[1:0] (low/low d efault) 00' for ss_en_tri = 0, '01' for ss_en_tri = 'm', '11 for ss_en_tri = '1' 00' = ss off, '01' = -0.25% ss, '10' = reserved, '11'= -0.5% ss reserved controls output amplitude reserved reserved reserved ref slew rate control see b11[1:0]
8-output 3.3v pcie clock generator 12 october 19, 2016 9fgl08 datasheet smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 1 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 0 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 1 bit 2 device id2 r 0 bit 1 device id1 r 0 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 bytes 8 and 9 are reserved. smbus table: pll mn enable, pd_restore byte 10 name control function type 0 1 default bit 7 pll m/n en 1 m/n programming enable rw m/n prog. disabled m/n prog. enabled 0 bit 6 power-down (pd) restore restore default config. in pd rw clear config in pd keep config in pd 1 bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x 1. this bit is a '1' on 9fgl0xp1 devices reserved 0001 = idt vendor id reserved reserved reserved b rev = 0001 revision id 001000 binary or 08 hex device id writing to this register will configure how many bytes will be read back, default is = 8 bytes. reserved byte count programming reserved reserved reserved 00 = fgx, 01 = dbx, 10 = dmx, 11= dbx w/opll device type reserved
october 19, 2016 13 8-output 3.3v pcie clock generator 9fgl08 datasheet smbus table: stop state control byte 11 name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 stp[1] rw 00 = low/low 10 = high/low 0 bit 0 stp[0] rw 01 = hiz/hiz 11 = low/high 0 smbus table: impedance control byte 12 name control function type 0 1 default bit 7 dif3_imp[1] dif3 zout rw bit 6 dif3_imp[0] dif3 zout rw bit 5 dif2_imp[1] dif2 zout rw bit 4 dif2_imp[0] dif2 zout rw bit 3 dif1_imp[1] dif1 zout rw bit 2 dif1_imp[0] dif1 zout rw bit 1 dif0_imp[1] dif0 zout rw bit 0 dif0_imp[0] dif0 zout rw note: each output defaults to '10' for 9dblxx41, and '01' for 9dblxx51. defaults for 9dblxxp1 parts are programmable. smbus table: impedance control byte 13 name control function type 0 1 default bit 7 dif7_imp[1] dif7 zout rw bit 6 dif7_imp[0] dif7 zout rw bit 5 dif6_imp[1] dif6 zout rw bit 4 dif6_imp[0] dif6 zout rw bit 3 dif5_imp[1] dif5 zout rw bit 2 dif5_imp[0] dif5 zout rw bit 1 dif4_imp[1] dif4 zout rw bit 0 dif4_imp[0] dif4 zout rw note: each output defaults to '10' for 9dblxx41, and '01' for 9dblxx51. defaults for 9dblxxp1 parts are programmable. smbus table: pull-up pull-down control byte 14 name control function type 0 1 default bit 7 oe3_pu/pd[1] rw 00=none 10=pup 0 bit 6 oe3_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 5 oe2_pu/pd[1] rw 00=none 10=pup 0 bit 4 oe2_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 3 oe1_pu/pd[1] rw 00=none 10=pup 0 bit 2 oe1_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 1 oe0_pu/pd[1] rw 00=none 10=pup 0 bit 0 oe0_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 reserved reserved reserved reserved true/complement dif output disable state oe3 pull-up(pup)/ pull-down(pdwn) control oe2 pull-up(pup)/ pull-down(pdwn) control oe1 pull-up(pup)/ pull-down(pdwn) control oe0 pull-up(pup)/ pull-down(pdwn) control 00=33ohm dif zout 01=85ohm dif zout 10=100ohm dif zout 11 = reserved 00=33ohm dif zout 01=85ohm dif zout 10=100ohm dif zout 11 = reserved reserved reserved see note see note
8-output 3.3v pcie clock generator 14 october 19, 2016 9fgl08 datasheet smbus table: pull-up pull-down control byte 15 name control function type 0 1 default bit 7 oe7_pu/pd[1] rw 00=none 10=pup 0 bit 6 oe7_pu/pd0] rw 01=pdwn 11 = pup+pdwn 1 bit 5 oe6_pu/pd[1] rw 00=none 10=pup 0 bit 4 oe6_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 3 oe5_pu/pd[1] rw 00=none 10=pup 0 bit 2 oe5_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 bit 1 oe4_pu/pd[1] rw 00=none 10=pup 0 bit 0 oe4_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 1 smbus table: pull-up pull-down control byte 16 name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 ckpwrgd_pd_pu/pd[1] rw 00=none 10=pup 1 bit 0 ckpwrgd_pd_pu/pd[0] rw 01=pdwn 11 = pup+pdwn 0 bytes 17 is reserved smbus table: polarity control byte 18 name control function type 0 1 default bit 7 oe7_polarity sets oe7 polarity rw enabled when low enabled when high 0 bit 6 oe6_polarity sets oe6 polarity rw enabled when low enabled when high 0 bit 5 oe5_polarity sets oe5 polarity rw enabled when low enabled when high 0 bit 4 oe4_polarity sets oe4 polarity rw enabled when low enabled when high 0 bit 3 oe3_polarity sets oe3 polarity rw enabled when low enabled when high 0 bit 2 oe2_polarity sets oe2 polarity rw enabled when low enabled when high 0 bit 1 oe1_polarity sets oe1 polarity rw enabled when low enabled when high 0 bit 0 oe0_polarity sets oe0 polarity rw enabled when low enabled when high 0 smbus table: polarity control byte 19 name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 ckpwrgd_pd determines ckpwrgd_pd polarity rw power down when low power down when high 0 reserved oe7 pull-up(pup)/ pull-down(pdwn) control oe6 pull-up(pup)/ pull-down(pdwn) control oe5 pull-up(pup)/ pull-down(pdwn) control oe4 pull-up(pup)/ pull-down(pdwn) control reserved reserved reserved reserved reserved ckpwrgd_pd pull-up(pup)/ pull-down(pdwn) control reserved reserved reserved reserved reserved reserved reserved
october 19, 2016 15 8-output 3.3v pcie clock generator 9fgl08 datasheet recommended crystal char acteristics ( 3225 package) marking diagrams notes: 1. ?lot? is the lot sequence number. 2. ?coo? denotes country of origin. 3. yyww is the last two digits of the year and week that the part was assembled. 4. line 2: truncated part number 5. ?l? denotes rohs compliant package. 6. ?i? denotes industrial temperature range device. 7. ?p? denotes factory programmable defaults thermal characteristics parameter value units notes frequency 25 mhz 1 resonance mode fundamental - 1 frequency tolerance @ 25c 20 ppm max 1 frequency stability, ref @ 25c over operating temperature range 20 ppm max 1 temperature range (commerical) 0~70 c 1 temperature range (industrial) -40~85 c 1 equivalent series resistance (esr) 50 ? 5 ppm max 1 notes: 1. fox 603-25-150 ics fgl0841bi yyww coo lot ics fgl0851bi yyww coo lot ics 08p1b000i yyww coo lot parameter symbol conditions pkg typ value units notes jc junction to case 33 c/w 1 c/w 1 junction to air, still air 37 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 26 c/w 1 1 epad soldered to board thermal resistance ndg48
8-output 3.3v pcie clock generator 16 october 19, 2016 9fgl08 datasheet package outline and package dimensions (ndg48)
october 19, 2016 17 8-output 3.3v pcie clock generator 9fgl08 datasheet package outline and pack age dimensions, cont. (ndg48)
8-output 3.3v pcie clock generator 18 october 19, 2016 9fgl08 datasheet ordering information ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. ?b? is the device revision designator (wil l not correlate with the datasheet revision). ?xxx? is a unique factory assigned number to identify a particular default configuration. revision history part / order number notes shipping packaging package temperature 9fgl0841bkilf trays 48-pin vfqfpn -40 to +85 c 9fgl0841bkilft tape and reel 48-pin vfqfpn -40 to +85 c 9FGL0851BKILF trays 48-pin vfqfpn -40 to +85 c 9FGL0851BKILFt tape and reel 48-pin vfqfpn -40 to +85 c 9fgl08p1bxxxkilf trays 48-pin vfqfpn -40 to +85 c 9fgl08p1bxxxkilft tape and reel 48-pin vfqfpn -40 to +85 c 100 ? 85 ? factory configurable. contact idt for addtional information. rev. issue date intiator description page # a 6/9/2015 rdw 1. updated electrical tables to final 2. updated power management table and smbus to final 3. updated pin description title 4. updated rs values in test loads 5. added note for byte 3, bit 4, changed definition of '0' condition. 6. updated ordering information for '000' part. 2-4, 6-9, 11, 18 b 7/17/2015 rdw 1. added voh and ioh to ref table. 2. minor formatting updates for readab ility and consistency. 3. added i-temp crystal part number to crystal characteristics table 4. added reference to an-891 for terminating to other logic fam ilies. 5. removed lvds termination drawing (now in an-891) various c 2/4/2016 rdw 1. updated ordering information to b rev 2. updated byte 5 3. udpated block diagram various d 6/3/2016 rdw 1. update electrical tables for b rev production release 2. added pcie sris and pcie gen4 cc to phase jitter tables. 3. updated front page text. 4. removed '000' blank device from ordering information. 5. updated byte0wording for clarity 6. updated byte1[1:0] descriptions. various e 6/28/2016 rdw 1. updated electrical tabels with final data from pe/te 2. changed typical power consumption to 206mw. 3. minor cleanup of the smbus descriptions. 4. release various f 10/19/2016 rdw removed idt crystal part number
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support

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